1. Field of the Invention
The present invention relates to a semiconductor device and a layout design apparatus of a semiconductor device. More particularly, the present invention relates to a semiconductor device including logic circuits having different power supply lines which are alternately connected to the logic circuits, and a layout design apparatus of the semiconductor device.
Priority is claimed on Japanese Patent Application First Publication, No. 2009-297750, filed Dec. 28, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
As an example of a general semiconductor device, an inverter circuit (INV) circuit, a MOS logic circuit, including N-channel MOS transistors (NMOS transistors) and P-channel MOS transistors (PMOS transistors) are shown in FIGS. 10A and 10B. FIG. 10A is a view illustrating an example of a layout of the inverter circuit. FIG. 10B is a view illustrating a circuit diagram of the inverter circuit. FIG. 10C is a view illustrating a symbol of the inverter circuit.
In FIG. 10A, the inverter circuit includes a PMOS transistor P1 and an NMOS transistor N1. The gate electrodes Gp of the PMOS transistor P1 and the gate electrodes On of the NMOS transistor N1 are coupled to a gate wiring Jg which is formed on an upper wiring layer The gate wiring Jg is not shown in the figure. The drain electrode Dp of the PMOS transistor P1 and the drain electrode Dn of the NMOS transistor N1 are connected to a drain wiring Jd.
The PMOS transistor P1 is formed in a diffusion layer 101. The source electrodes of the PMOS transistor P1 is coupled to a power source line (VCC) through wiring layers M1n and Via-1. The drain electrode Dp of the PMOS transistor P1 is coupled to the drain electrode Dn of the NMOS transistor N1. The power source line may be referred to as a power supply line. The source electrodes of the NMOS transistor N1 are connected to a ground line GND (VSS) through wiring layers M1p and Via-2.
FIG. 11A is a view illustrating a layout of two inverter circuits INV1 and INV2 for forming a series connection of the inverter circuits INV1 and INV2. The inverter circuits INV1 and INV2 are adjacently formed. The inverter circuit INV1 includes a PMOS transistor P1 and an NMOS transistor N1. The inverter circuit INV2 includes a PMOS transistor P2 and an NMOS transistor N2. QP1 indicates a source diffusion layer of the PMOS transistor P1. QN1 indicates a source diffusion layer of the NMOS transistor N1. Further, QP2 indicates a source diffusion layer of the PMOS transistor P2. QN2 indicates a source diffusion layer of the NMOS transistor N2. In the figure, the source diffusion layers QP1 and QP2 are adjacent, and the source diffusion layers QN1 and QN2 are adjacent.
FIG. 11B is a view illustrating an example of a layout of the inverter circuits INV1 and INV2 in a reduced layout area of the inverter circuits INV1 and INV2. A diffusion layer QP1 (QP2) is used for the diffusion layer QP1 of the PMOS transistor P1 and the diffusion layer QP2 of the PMOS transistor P2. The diffusion layer QP1(QP2) may be referred to as a common diffusion layer QP1(QP2). A diffusion layer QN1(QN2) is used for the diffusion layer QN1 of the NMOS transistor N1 and the diffusion layer QN2 of the NMOS transistor N2. The diffusion layer QN1(QN2) may be referred to as a common diffusion layer QN1(QN2). Further, the common diffusion layer QP1(QP2) is connected to a wiring M1(Sp12), and the common diffusion layer QN1(QN2) is connected to a wiring M1(Sn12). In this way, a common diffusion layer is used for the diffusion layers of adjacent sources. The diffusion layers to be connected to the power source of the inverter circuits INV1 and INV2 are coupled to another common diffusion layer. Thereby, the total layout area of inverter circuits INV1 and INV2 can be reduced. FIG. 11C indicates a symbol of the inverter circuits formed in series connections.
There is another type of logic circuits in which series-connected logic circuits of a semiconductor device are driven by different power source lines. In this case, the different power source lines are alternately coupled to the series-connected logic circuits. Recently, this type of power supply configuration is increasingly used for semiconductor devices, such as DRAMs (dynamic random access memories), since they are installed in a mobile device or the like. Namely, such logic circuits can be used for reducing current consumption of the semiconductor devices.
In this case, the logic circuits include a sub-power source line and a sub-ground line (GND) in addition to a primary power source line and a primary ground line. The sub-power source line is coupled to a sub-power supply providing a sub-voltage (sub-electrical potential). The sub-ground line (GND) is coupled to a sub-ground supply which provides a sub-ground potential. The primary power source line is coupled to a primary voltage supply which provides a primary electrical potential. The primary ground line is coupled to a primary ground supply which provides a primary ground potential. Japanese Patent Application First Publication, No. 2007-324409 and United States Patent Application, Publication No. 2007-0278528, describe that the sub-power source line enables MOS transistors to reduce current consumption of the sub-threshold current of MOS transistors. Such power supply system, which provides different power supply lines for the circuits, may be referred to as a current source control configuration.